Semiconductor device including passivation layer encapsulant

ABSTRACT

A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

DOMESTIC PRIORITY

This application is a division of application Ser. No. 14/202,067,entitled “SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT”,filed on Mar. 10, 2014, which is a continuation-in-part of applicationSer. No. 13/873,801, entitled “STRUCTURES AND METHODS TO REDUCE MAXIMUMCURRENT DENSITY IN A SOLDER BALL”, filed on Apr. 30, 2013, now Pat. No.8,674,506, which is a division of application Ser. No. 12/640,752,entitled “STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN ASOLDER BALL”, filed on Dec. 17, 2009, now Pat. No. 8,446,006, and whichthe entire disclosures of all above-reference applications are herebybeing incorporated by reference.

BACKGROUND

Conventional far back-end-of-line (FBEOL) processes for fabricatingsmaller scaled semiconductor devices (e.g., 32 nm and 22 nm) usealuminum pads that support a controlled collapse chip connection (C4)element and the corresponding underbump metallurgy (UBM). As dimensionsof features (e.g., pads, wires, interconnects, vias, etc.) continue toshrink to create smaller devices, the maximum allowable current densitydecreases rapidly due to element electromigration (EM) effects. Thiscrowding of current associated with the C4 and the aluminum pad and/orvia structures often results in EM void formation, which can lead toincreased resistance that negatively affects the performance of thesemiconductor device

SUMMARY

According to at least one embodiment, a method of fabricating asemiconductor device includes forming a passivation layer on a least onecapping layer of the semiconductor device, and forming an encapsulantlayer on the passivation layer. The method further includes patterningthe encapsulant layer to expose a portion of the passivation layer andforming a final via opening in the passivation layer. A conductivematerial is deposited in the final via opening. The method furtherincludes planarizing the conductive material until reaching a remainingportion of the encapsulant layer such that the conductive material isflush with the encapsulant layer and the passivation layer is preserved.

According to another embodiment, a method of fabricating a semiconductordevice includes forming a passivation layer on a least one capping layerof the semiconductor device, and forming an encapsulant layer on thepassivation layer. The method further includes patterning theencapsulant layer to expose a portion of the passivation layer andforming a final via opening in the passivation layer. A conductivematerial is deposited in the final via opening. The method furtherincludes planarizing the conductive material until reaching a remainingportion of the encapsulant layer such that the conductive material isflush with the encapsulant layer and the passivation layer is preserved.

According to another embodiment, a semiconductor device comprises apassivation layer formed on at least one capping layer of thesemiconductor device. An encapsulant layer is formed on the passivationlayer, and a final via opening is formed in the passivation layer. Aconductive material is deposited in the final via opening. Theconductive material is flush with an upper surface of the encapsulantlayer. The passivation layer has at least one preserved surface that isdisposed against the encapsulant layer. The at least one preservedsurface excluding at least one etched deformity.

Additional features are realized through the techniques of the presentinvention. Other embodiments are described in detail herein and areconsidered a part of the claimed invention. For a better understandingof the invention with the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing features are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 is a cross-sectional view of a starting substrate including afilm cap formed on contact pads disposed in a dielectric layer, andcapping layers formed on an upper surface of the film cap;

FIG. 2 illustrates the substrate of FIG. 1 following a first etchingprocess that forms terminal via openings in the capping layers to exposean upper surface of the film cap;

FIG. 3 illustrates the substrate of FIG. 2 after depositing apassivation layer on an upper surface of the capping layer and in theterminal via openings;

FIG. 4 illustrates the substrate of FIG. 3 after forming an encapsulantlayer on an upper surface of the passivation layer;

FIG. 5 illustrates the substrate of FIG. 4 after patterning theencapsulant layer to expose a portion of the underlying passivationlayer;

FIG. 6 illustrates the substrate of FIG. 5 following a second etchingprocess that forms a first via opening in the passivation layer and thatremoves the passivation layer material from the terminal via openings;

FIG. 7 illustrates the substrate of FIG. 6 following a third etchingprocess that etches through the film cap and stops on the contact pads;

FIG. 8 illustrates the substrate of FIG. 7 after depositing a conductiveliner that conforms to an upper surface of the encapsulant layer and tothe surfaces of the passivation layer, capping layers and contact padsdefined by the final via opening and the terminal via openings,respectively;

FIG. 9 illustrates the substrate of FIG. 8 after depositing a conductivematerial that fills the final via opening and the terminal via openings,and that covers the uppers surfaces of the passivation layer and theencapsulant layer; and

FIG. 10 illustrates the substrate of FIG. 9 following a planarizationprocess that planarizes the conductive material and stops on theencapsulant layer.

DETAILED DESCRIPTION

With reference now to FIG. 1, a starting substrate 100 of is illustratedaccording to an exemplary embodiment. The starting substrate 100includes a dielectric layer 102, a film cap 104, and one or more cappinglayers 106. The dielectric layer 102 is formed from a dielectricmaterial including, but not limited to, doped silicon carbide, siliconnitride, low-k materials, TEOS, FTEOS, etc. According to at least oneexemplary embodiment, a contact pad 108 is disposed in dielectric layer104. The contact pad 108 is formed from any suitable conducting materialincluding, but not limited to, copper, copper alloy, aluminum, etc. Thecontact pad 108 is formed in the dielectric layer 102 using one or moreconventional semiconductor processing techniques, such as, for example,photolithography and reactive ion etch (RIE), chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), and atomiclayer deposition (ALD). According to at least one embodiment, anelectrically conductive contact liner 109 is interposed between arespective contact pad 108 and the dielectric layer 102. The contactliner 109 is formed from one or more materials including, but notlimited to, tantalum nitride (TaN), cobalt (Co), cobalt manganese(CoMn), titanium (Ti), titanium tungsten (TiW) and ruthenium (Ru).Various methods for depositing the contact liner 109 may be usedincluding, but not limited to, plasma sputtering, evaporation, ALD andCVD.

The film cap 104 is formed on the dielectric layer 102 and contact pad108. In embodiments, the film cap 104 is composed of silicon nitride(SiN_(x)) or a well-known composition referred to as NBLoK (e.g.,SiC(N,H), or SN_(x)C_(y)H_(z)) deposited using conventional processessuch as CVD, PECVD, ALD, etc. The film cap 104 may have any desiredthickness (e.g., depth). The invention is not limited to the exemplarymaterials and processes described herein, and other materials and/orprocesses may be used to form the film cap 104 within the scope of theinvention.

According to at least one exemplary embodiment, the capping layers 106include a first capping layer 110 and a second capping layer 112. Thefirst capping layer 110 is formed on the film cap 104 and is formedfrom, for example, silicon oxide (SiO_(x)). It appreciated, however,that other oxide materials may be used to form the first capping layer110. The first capping layer 110 is deposited using various methodsincluding, but not limited to, CVD, PECVD, ALD, etc. The first cappinglayer 110 has various thicknesses according to the desired applicationof the semiconductor device.

The second capping layer 112 is formed on the first capping layer 110,and is formed from, for example, SiN_(x). Accordingly, the first cappinglayer 110 is interposed between the film cap 104 and the second cappinglayer 112. Although SiN_(x) is an exemplary material for forming thesecond capping layer 112, it is appreciated that other nitride materialsmay be used. The second capping layer 112 is deposited using variousmethods including, but not limited to, CVD, PECVD, ALD, etc. The secondcapping layer 112 has various thicknesses according to the desiredapplication of the semiconductor device.

Referring to FIG. 2, one or more via openings 114 (e.g., terminal viaopenings) are formed in the first capping layer 110 and the secondcapping layer 112. The via openings 114 may be formed using a RIEprocess, for example, that is selective to the material (e.g., nitride)of the film cap 104. In this regard, the via openings 114 are etchedthrough the first and second capping layers 110, 112 and stop on thefilm cap 104.

Turning to FIG. 3, a passivation layer 116 is formed on the secondcapping layer 112 and fills the via openings 114. According to at leastone embodiment, the passivation layer 116 is composed of photosensitivepolyimide (PSPI) and is deposited using conventional processes such, forexample, as spin coating. The passivation layer 116 may be cured (e.g.,baked) in order to toughen the passivation layer 116 (i.e., the PSPI),as understood by those ordinarily skilled in the art. The passivationlayer 116 may have any desired thickness (e.g., depth). The invention isnot limited to the exemplary materials and processes described herein,and other materials and/or processes may be used to form the passivationlayer 116 within the scope of the invention, such as curtain coatings ofother polymer passivation materials.

Referring now to FIG. 4, an encapsulant layer 118 is formed on an upperportion of the passivation layer 116. The encapsulant layer 118 isformed from, for example, silicon nitride (SiN_(x)) and is depositedaccording to various deposition methods including, but not limited to,CVD, PECVD and ALD. The encapsulant layer 118 has a thickness of, forexample, approximately 1000 angstroms (A), and is configured to protectthe passivation layer 116 during one or more subsequent process (e.g.,chemical mechanical planarization), as described in greater detailbelow. According to at least one exemplary embodiment, the thickness ofthe encapsulant layer 118 is greater than a thickness of the film cap104.

Turning now to FIG. 5, the encapsulant layer 118 is patterned to form anopening 120 that exposes a portion of the underlying passivation layer116. According to an embodiment, a conventional lithograph and RIEtechnique is used to form the opening 120 when the encapsulant layer 118is thick, e.g., approximately 1000 A or greater.

According to another embodiment, a laser-masking ablation process isused to form the opening 120 when the encapsulant layer 118 is thin,e.g., approximately 500 A. In this regard, a patterned mask (not shown)formed from, for example, aluminum quartz, is interposed between a laserablation tool and the encapsulant layer 118. The mask is patternedaccording to a desired patterning (e.g., opening 120) to be formed inthe encapsulant layer 118. High energy pulses are generated by the laserablation tools, and are delivered to the encapsulant layer 118 via thepatterning of the mask. The pulsed energy heats and ablates theencapsulant layer 118. Accordingly, the desired pattern is formed in theencapsulation layer 118, thereby exposing the underlying passivationlayer 116. The energy pulses are generated at wavelength of, forexample, 308 nanometers (nm) UV energy, and include a range of fluencesfrom approximately 0.1 to approximately 2.0 joules per squarecentimeter. The pulses have a duration ranging, for example, fromapproximately 15 nanoseconds (ns) to approximately 25 ns. Although anexemplary wavelength of 308 nm is described above, it is appreciatedthat the wavelength of the UV pulses includes all wavelengths producedby an excimer laser (i.e., exciplex laser) without limitation. Forexample, the UV energy pulses may range from approximately 126 nm toapproximately 351 nm.

Turning to FIG. 6, a first via etching process is performed which formsat least one final via (FV) opening 122 in the passivation layer 116.The first via etching process also removes the passivation layer 116deposited in the via openings 114. The first via etch process isselective to the cap film 104 and the encapsulant layer 118. In thisregard, a portion of the passivation layer 116 located beneath theencapsulant layer 118 is preserved (i.e., not etched) and a portion ofthe cap film 104 is exposed by a respective via opening 114. The firstvia etching process may be performed according to either a conventionallithograph and subsequent RIE process, or a laser-masking ablationprocess similar to the processes discussed above. If laser ablationprocess is used and the encapsulant layer is thin, e.g., less than 1000A then the buffer regions 123 are created such that the laser beam usedto create the via by ablating the passivation material doesn't causelocalized heating and subsequent damage of the thin encapsulant close tothe via opening. According to one embodiment, opposing walls of thefinal via opening 122 formed according to the laser-masking ablationprocess have an angle being less than 90 degrees with respect to the atleast one capping layer, and the opposing walls are uniform with respectto one another.

According to at least one embodiment, opposing buffer regions 123 areformed in the passivation layer 116 as further illustrated in FIG. 6.The buffer regions 123 are formed, for example, by performing alaser-masking ablation process that uses a mask (e.g., an aluminumquartz mask). The mask (not shown) includes a pattern configured to forma desired FV opening (e.g., FV opening 122) in the passivation layer116. The mask may include a solid portion that covers a portion of thepassivation layer 116 extending between respective patterned edges ofthe encapsulant layer 118 to the edge of the FV opening 122. The coveredportion, therefore, defines the formed buffer regions 123. The bufferregions 123 may have a length ranging from, for example, approximately 2nm to approximately 3 nm.

Referring now to FIG. 7, a second via etching process is performed whichremoves the cap film 104 exposed by a respective via openings 104.Accordingly, a portion of the underlying contact pad 108 is exposed. Thesecond via etching process is performed, for example, using a RIEprocess that is selective to the passivation layer 112 and the cappinglayers 106. The film cap 104 and the encapsulant layer 118 aresimultaneously etched. However, the encapsulant layer has thickness thatis greater than the thickness of the film cap 104. In this regard, thefilm cap 104 is removed while the thickness of the encapsulant layer 118remains with a reduced thickness.

Turning to FIG. 8, an electrically conductive liner 124 is formed on thesurfaces of the encapsulant layer 118 and passivation layer 116. Theconductive liner 124 also conforms to exposed surfaces of the cappinglayer 106 and the contact pads 108 defined by the FV opening 122 and thevia openings 114, respectively. The conductive liner 124 is formed fromone or more materials including, but not limited to, tantalum nitride(TaN), cobalt (Co), cobalt manganese (CoMn), titanium (Ti), titaniumtungsten (TiW) and ruthenium (Ru). Various methods for depositing theconductive liner 124 may be used including, but not limited to, plasmasputtering, evaporation, ALD and CVD.

Referring to FIG. 9, a conductive material 126 is deposited on theconductive liner 124. According to at least one embodiment, theconductive material 126 fills the via openings 114 and FV opening 122,and covers the upper surfaces of the passivation layer 116 andencapsulant layer 118. The conductive material 126 is formed usingvarious processes including, for example, electroplating, and isannealed as understood by those ordinarily skilled in the art. Accordingto one exemplary embodiment, the conductive material 126 is anelectroplating material such as, for example, copper (Cu). It isappreciated, however, that the conductive material may comprise otherconductive materials including, but not limited to, copper manganese(CuMn), gold (Au) and tin (Sn).

Turning now to FIG. 10, excess conductive material 126 is planarizedusing a chemical planarization (CMP) process, for example. Theencapsulant layer 118 acts as an etch stop (e.g., a CMP stop layer) thatalso protects the underlying passivation layer 116 from being recessedduring the CMP process. That is, the CMP process stops on theencapsulant layer 118 such that the upper surface of the conductivematerial 126 is formed flush with the upper surface of the encapsulantlayer 118, while the underlying passivation layer 116 is unaffected andpreserved. As further illustrated in FIG. 10, the passivation layer hasa preserved surface 128 that is disposed against the encapsulant layer118. Since the encapsulant layer 118 protects the passivation layer 116from the CMP process, the at least one preserved surface excludes atleast one etched deformity which can result when being exposed to theCMP result.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of onemore other features, integers, steps, operations, element components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the inventive teachings and the practical application, andto enable others of ordinary skill in the art to understand theinvention for various embodiments with various modifications as aresuited to the particular use contemplated.

There may be many variations to this diagram or the operations describedtherein without departing from the spirit of the invention. Forinstance, the operations may be performed in a differing order oroperations may be added, deleted or modified. All of these variationsare considered a part of the claimed invention.

While various embodiments have been described, it will be understoodthat those skilled in the art, both now and in the future, may makevarious modifications which fall within the scope of the claims whichfollow. These claims should be construed to maintain the properprotection for the invention first described.

What is claimed is:
 1. A semiconductor device comprising: a passivationlayer formed on at least one capping layer of the semiconductor device;an encapsulant layer formed on the passivation layer, the passivationlayer including opposing buffer regions; final via opening formed in thepassivation layer and between the opposing buffer regions such that thebuffer regions define the outer periphery of the final via opening; anda conductive material deposited in the final via opening, the conductivematerial including an upper surface being flush with an upper surface ofthe encapsulant layer, wherein the passivation layer has at least onepreserved surface that is disposed against the encapsulant layer, the atleast one preserved surface excluding at least one etched deformity. 2.The semiconductor device of claim 1, wherein the encapsulant layer isformed from a nitride material that is resistant to thechemical-mechanical planarization process.
 3. The semiconductor deviceof claim 2, further comprising a conductive liner formed on an uppersurface and sidewalls of the passivation layer, and an upper surface ofthe at least one capping layer defined by the final via opening.
 4. Thesemiconductor device of claim 3, wherein the conductive material is anelectroplating material formed on the conductive liner, theelectroplating material filling the final via opening and covering theencapsulant layer.
 5. The semiconductor device of claim 4, wherein anupper surface of the encapsulant layer excludes the conductive liner andis flush with the electroplating material.
 6. The semiconductor deviceof claim 5, further comprising: a film cap that covers at least onecontact pad disposed in a dielectric layer of the semiconductor devicethe at least one capping layer formed on the film cap; and at least oneterminal via opening formed in the at least one capping layer prior, theelectroplating material filling the least one terminal via opening toform at least one electrically conductive terminal via that contacts theelectroplating material and the at least one contact pad.
 7. Thesemiconductor device of claim 6, wherein the encapsulant layer has athickness of no less than 1000 angstroms, and a patterned edge of theencapsulant layer extends completely to an edge of the final viaopening.
 8. The semiconductor device of claim 7, wherein opposing wallsof the final via opening have an angle being less than 90 degrees withrespect to the at least one capping layer, the opposing walls beinguniform with respect to one another.
 9. The semiconductor device ofclaim 8, wherein the opposing buffer regions are interposed between apatterned edge of the encapsulant prior and the final via opening. 10.The semiconductor device of claim 5, wherein an extended portion of theconductive liner is deposited on an upper surface of each buffer region.11. The semiconductor device of claim 10, wherein the extended portionof the conductive liner is interposed between a respective buffer regionand the conductive material so as to couple the conductive liner and theconductive material to the passivation layer.
 12. The semiconductordevice of claim 11, wherein the conductive liner and the conductivematerial are each excluded from an upper surface of the at least onepreserved surface.